1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to multi-chip mounting structures and underfills and methods of assembling the same.
2. Description of the Related Art
A conventional type of multi-chip module includes two semiconductor chips mounted side-by-side on a carrier substrate or interposer. The semiconductor chips are flip-chip mounted to the interposer and interconnected thereto by respective pluralities of solder joints. The interposer is provided with plural electrical pathways to provide input/output pathways for the semiconductor chips both for inter-chip power, ground and signal propagation as well as input/output from the interposer itself. The semiconductor chips include respective underfill material layers to lessen the effects of differential thermal expansion due to differences in the coefficients of thermal expansion of the chips, the interposer and the solder joints.
A conventional method for fabricating the aforementioned conventional multi-chip module includes flip-chip mounting the first of the two semiconductor chips on the interposer and dispensing an underfill between the first mounted chip and the interposer. The underfill migrates laterally between the chip and the interposer and, upon thermal cure, produces a fillet that extends beyond the periphery of the semiconductor chip. Thereafter, the second semiconductor chip is flip-chip mounted to the interposer and a second underfill is positioned between the second mounted semiconductor chip and the interposer. Following a second thermal cure, the second underfill produces another fillet that extends beyond the periphery of the second semiconductor chip and typically abuts against the fillet of the first underfill of the first semiconductor chip.
A conventional set of design rules for manufacturing the aforementioned conventional multi-chip module has to account for the respective widths of the underfill material layer fillets. Thus, the fillets themselves present a constraint on the minimum permissible spacing between the two adjacent semiconductor chips. As with many aspects of semiconductor chip and package design, a constraint on the miniaturization of conductor structures, such as the conductive pathways between the semiconductor chips of the module, presents a limit on the amount of reduction in signal latency and perhaps power consumption due to resistive losses and other issues associated with line length.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.